This invention relates to computer systems and, more particular, to methods and apparatus for providing high output voltage level with a low level input voltage by using charge pump circuitry.
A major trend in the manufacture of personal computers is toward portable computers which are able to provide most of the abilities of desktop computers. However, in order to accomplish this goal, such portable computers must provide large storage capacity and high processor speed necessary to run large programs. A typical prior art portable computer uses a great deal of power in order to meet these requirements.
At the same time, computer designers are modifying the components used in such portable computers so that the portable computers are able to run for long periods while consuming very small amounts of power. In order to reduce power consumption and extend battery life, much of the integrated circuitry used in portable computers is being redesigned to run at low voltage levels. This reduces the power usage and allows more components to be placed closer to one another in the circuitry. Currently, circuitry and components used in portable computers are being designed to operate at very low voltage levels such as 3.3 volts. However, due to continuous developments in this area, the next generation's portable computers are being designed to run at a voltage of less than 2.0 volts in order to further reduce the power consumptions.
However, at the same time, the desire to make portable computers offering all of the advantages of desktop computers opposes this salutary result. Many of the advantages offered by desktop computers require higher voltages in order to function. For example, one real convenience is the ability to change the BIOS processes as improvements in the computer or its peripherals occur. Historically, this has been accomplished by removing the electrical programmable read only memory (EPROM) for storing the BIOS processes and replacing it with new circuitry at additional cost. This is a complicated operation beyond the abilities of many computer users. Recently, electrically erasable programmable read only memory (EEPROM) has been used to store the BIOS processes in some newly designed portable computers. These computers run a small update program to reprogram the BIOS circuitry when the user changes the BIOS processes. However, reprogramming the EEPROM sometimes requires up to about fifteen to twenty volts to accomplish.
Another form of EEPROM array provides another example of high voltage requirements in portable computers. Recently, a new form of long term random access storage has been devised using EEPROM technologies. For example, an array of large capacity EEPROM may be used in place of a hard disk drive. This EEPROM array provides a smaller lighter functional equivalent of a hard disk drive which operates more rapidly and is not as sensitive to physical damage as the hard disk. Such memory arrays are especially useful in portable computers where space is at a premium and weight is extremely important. However, these EEPROM arrays also require much higher voltages for writing and erasing of data.
In the process of writing and erasing of data in the EEPROM, it is well known in the art that a voltage regulator is needed to supply the high voltage level. In the integrated circuit environment, usually a charge pump circuitry is employed as the voltage regulator to provide the high voltage level.
Experimental results have shown that the speed of the writing and erasing of data in the EEPROM is directly related to the supplied voltage level. The higher the supplied voltage level, the faster the writing and erasing of data in the EEPROM. Therefore, the designers have been continuously working to increase the voltage output level from the voltage regulator.
In addition, in order to satisfy most system requirements, the charge pump circuitry must be able to supply unregulated voltages close to the breakdown of the process so that erase/write times will be in the few millisecond range. The prior art charge pump architecture requires that a minimum VDD level of about 3.0 volts be used to provide this high voltage. Unfortunately, due to the continuous need of reducing the power consumption, the marketplace is demanding the next generation charge pump circuitry to work with VDD levels in the 2.0 volts range because of the concern of the overall power consumption and system performance.
The conventional approach used for creating the high voltage level is based upon a classic diode scheme using NMOS FETs. The circuitry is shown on FIGS. 1-2 and consists of several individual diode pump units 10a, 10b . . . connected in series to form a serial diode pump chain 20. Each of the diode pump units is composed of a NMOS FET 110 and a capacitor 120 as shown in FIG. 2. The drain and the gate of each of the NMOS FET 110 are connected together as shown in FIG. 2 wherein the resulting NMOS FET 110 works in a diode-like manner such that the current is cramped to flow only in one direction (i.e. from drain to source). Therefore, at the end of each clock cycle, the charges in each of the diode pump units are forced to be accumulated in the capacitor 120. In the illustrated example, there are 22 active diode pump units 10a, 10b, . . . and 1 holding stage 30. This diode pump chain has the VDD as its input along with clock signals (CLKB 40, CLKZ 50) which are the inverse of each other and transition from VDD to GND. The holding stage 30 isolates the output voltage from the clock signals and maintains the output voltage steady.
Before the details of the pumper are explained, it is necessary to define some terms. VDD is the chip supply voltage, Vt is the threshold of the NMOS devices, and Vsbnx is the source body effect of the Xth NMOS device and is a function of the voltage on the node (N1 or N2 . . . Nx).
The basic operation of the charge pump chain 20 is such that when CLKB 40 is at GND, the node N1 is charged to .about.(VDD-Vt-Vsbn1). After node N1 is charged to this value, the CLKB 40 signal rises to a VDD level and causes N1 to boost to .about.(2VDD-Vt-Vsbn1). During this boost time, CLKZ 50 is at GND and part of the voltage created at N1 is passed to node N2. Specifically, node N2 will charge up to .about.2(VDD-Vt)-Vsbn1-Vsbn2. Now, CLKB 40 goes back to GND while CLKZ 50 rises to a VDD. This causes node N2 to rise and subsequently forces node N3 to a higher value consistent with the charge/boost terms noted above. This charge/boost process continues up the chain causing each node (Nx) to be a higher level than the previous nodes until the HVOUT node reaches the voltage desired.
The problem facing this basic approach is that the Vsbnx term is a function of the nodal location (N1, N2, . . . etc.) within the charge pump chain. The Vsbnx of the higher nodes (i.e., N21) is significantly higher than the Vsb value for N1. In order for the charge pump circuitry to operate and not become current starved, it is necessary that the following relationship be satisfied: EQU VDD&gt;Vt+Vsbnx
Since Vt is fixed and Vsbnx varies by location, it is clear that the inequality may not be satisfied if VDD is too low or there are too many diode pump stages.
The conventional design architecture (using a VDD level of 2.0 volts) is theoretically limited (as per the equation above) to providing only 17.5 volts before the charge pump current starves (inequality not satisfied) and ceases operation. In reality, there are losses in circuits that interfaces with this charge pump that require VDD to be higher than this 2.0 volts. In fact, the existing design requires a minimum VDD level of close to 2.6 volts.